1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit, and in particular, to an internal clock signal driver circuit of the semiconductor integrated circuit.
2. Related Art
A conventional DLL clock signal driver receives a rising clock signal ‘RCK’ and a falling clock signal ‘FCK’, and generates a rising DLL clock signal ‘RCKDLL’ and a falling DLL clock signal ‘FCKDLL’ each having a predetermined pulse width.
As shown in FIG. 1, a conventional DLL clock signal driver includes a first pulse generating block 10 that generates the rising DLL clock signal ‘RCKDLL’, and a second pulse generating block 20 that generates the falling DLL clock signal ‘FCKDLL’.
The first pulse generating block 10 includes a first delay unit 11, first and second inverters IV1 and IV2, and a NAND gate ND1. The first delay unit 11 receives and delays the rising clock signal ‘RCK’, and the first inverter IV1 inverts the output signal of the first delay unit 11. The NAND gate ND1 receives the rising clock signal ‘RCK’ and the output signal of the first inverter IV1, and performs a NAND operation. The second inverter IV2 inverts the output signal of the NAND gate ND1.
Similarly to the first pulse generating block 10, the second pulse generating block 20 includes a second delay unit 22, third and fourth inverters IV3 and IV4, and a NAND gate ND2. The second pulse generating block 20 is different from the first pulse generating block 10 in that the falling clock signal ‘FCK’ is input as an input signal.
Here, as shown in FIG. 2, the rising DLL clock signal ‘RCKDLL’ and the falling DLL clock signal ‘FCKDLL’ should not overlap each other. In addition, the rising DLL clock signal ‘RCKDLL’ and the falling DLL clock signal ‘FCKDLL’ have a pulse width smaller than the rising clock signal ‘RCK’ and the falling clock signal ‘FCK’.
Generally, the DLL clock signal is basically driven on the conditions that the rising DLL clock signal ‘RCKDLL’ at the rising edge and the falling DLL clock signal ‘FCKDLL’ at the falling edge should not overlap each other, and the rising edges of the DLL clock signals ‘RCKDLL’ and ‘FCKDLL’ should be maintained. If any one of the two conditions is not satisfied, then the data ‘DQ’ and the data strobe signal ‘DQS’ of the semiconductor integrated circuit, which are output according to the rising DLL clock signal ‘RCKDLL’ and the falling DLL clock signal ‘FCKDLL’, can be distorted. If this occurs, then the semiconductor integrated circuit can not operate normally at high frequency.
Here, the rising clock signal ‘RCK’ and the falling clock signal ‘FCK’ as the input signals can have effective values enough to generate the DLL clocks ‘RCKDLL’ and ‘FCKDLL’ at the rising edges thereof. In addition, the pulse widths of the rising clock signal ‘RCK’ and the falling clock signal ‘FCK’ can vary, and even the two clock signals ‘RCK’ and ‘FCK’ can overlap each other. For this reason, the rising DLL clock signal ‘RCKDLL’ and the falling DLL clock signal ‘FCKDLL’, which are generated based on the rising and falling clocks ‘RCK’ and ‘FCK’, can overlap each other. However, a conventional DLL clock signal driver internally generates pulses having a prescribed width and uses the generated pulses. Accordingly, if the operation frequency is low, then the DLL clocks ‘RCKDLL’ and ‘FCKDLL’ do not overlap each other, and also the rising edges of the DLL clocks ‘RCKDLL’ and ‘FCKDLL’ are well maintained.
Meanwhile, in a conventional DLL clock signal driver, the pulse widths of the rising clock signal ‘RCK’ and the falling clock signal ‘FCK’ as the input signals are adjusted by the delay units 11 and 22 therein. Accordingly, the pulse widths of the rising clock signal ‘RCK’ and the falling clock signal ‘FCK’ can be the same or can be smaller than a prescribed width. At this moment, the output signals can be distorted and can overlap each other.
To solve these problems, as shown in FIG. 3, a conventional DLL clock signal driver having a latch block has been proposed.
A DLL clock signal driver circuit shown in FIG. 3 includes a first pulse generating block 30, a second pulse generating block 40, a first latch block 50, and a second latch block 60.
The first and second pulse generating blocks 30 and 40 have the same configuration as the first and second pulse generating blocks 10 and 20 shown in FIG. 1. The first latch block 50 includes third and fourth NAND gates ND3 and ND4, and a fifth inverter IV5, while the second latch block 60 includes fifth and sixth NAND gates ND5 and ND6, and a sixth inverter IV6.
The DLL clock signal driver shown in FIG. 3 is used for a semiconductor integrated circuit driving a high frequency band, and the outputs of the first and second pulse generating blocks 30 and 40 are input to the first and second latch blocks 50 and 60.
FIG. 4 is a timing chart of the DLL clock signal driver circuit shown in FIG. 3.
The output ‘RCKPB’ of the first pulse generating block 30 is disabled when the rising clock signal ‘RCK’ is enabled, and is enabled when the delayed rising clock signal ‘RCKDB’ is disabled. In addition, the output ‘FCKPB’ of the second pulse generating block 40 is disabled when the falling clock signal ‘FCK’ is enabled, and is enabled when the delayed falling clock signal ‘FCKDB’ is disabled.
The rising DLL clock signal ‘RCKDLL’ is enabled when the output ‘RCKPB’ of the first pulse generating block 30 is disabled, and is disabled when the output ‘FCKPB’ of the second pulse generating block 40 is disabled.
The falling DLL clock signal ‘FCKDLL’ is enabled when the output ‘FCKPB’ of the second pulse generating block 40 is disabled, and is disabled when the output ‘RCKPB’ of the first pulse generating block 30 is disabled.
However, the DLL clock signal driver shown in FIG. 3 also internally generates the pulses during a predetermined period, although the limited region, by the given pulse generating blocks 30 and 40. That is, the DLL clock signal drivers shown in FIGS. 1 and 3 internally generate the pulses based on the input signals ‘RCK’ and ‘FCK’ to prevent the DLL clocks ‘RCKDLL’ and ‘FCKDLL’ from overlapping each other and to maintain the rising edges. In this way, if the pulses are internally generated, then the operation can be secured within a frequency range until the widths of the input signals ‘RCK’ and ‘FCK’ and the widths of the internal pulses are the same. When the widths of the input signals ‘RCK’ and ‘FCK’ are smaller than the widths of the internal pulses, the output data can be distorted.
A conventional DLL clock signal driver has frequency limitations, and when the transistors have low performance, the rising and falling slopes of the internal pulses are increased. Then, the complete pulses can not be generated and in the worst case, the pulses can be lost, which can result in an erroneous operation.
In addition, since the wires through which the rising DLL clock signal ‘RCKDLL’ and the falling DLL clock signal ‘FCKDLL’ are transmitted are arranged over the entire semiconductor integrated circuit, they are affected by parasitic capacitance. Furthermore, when the characteristics of the transistors are changed due to the process parameters, the rising time and the falling time of the rising DLL clock signal ‘RCKDLL’ and the falling DLL clock signal ‘FCKDLL’ are extended (the level change speed of the signals become slower). In this case, the pulse widths of the rising DLL clock signal ‘RCKDLL’ and the falling DLL clock signal ‘FCKDLL’ can not be present.